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Table 35. Offset and Gain Correction
Calculation Type
Offset corrected
Corrected Sample
N ? ? N X ? N VSS ?
Absolute Voltage
Offset and gain corrected using VREF,
normalized to VREF
N ?
? N X ? N VSS ? ?? 16
? N VREF ? N VSS ?
V ?
( N ? VREF )
2 16
Offset and gain corrected using VDD,
normalized to VDD
N ?
? N X ? N VSS ? ?? 16
2 ? ? N VDD ? N VSS ?
V ?
( N ? VDD )
2 16
Equation notes
?
?
?
?
?
?
?
?
All N are 16-bit numbers.
N X is a sampling of the desired analog source.
N VSS is a sampling of ground. Due to the nature of the ADC's internal design, ground does not yield 0x0000
in the ADC_DATA register. Instead, ground yields a value closer to 1/3 of the range—for example, 0x5200.
N VREF is a sampling of VREF. Due to the nature of the ADC's internal design, VREF does not yield 0xFFFF in
the ADC_DATA register. Instead, VREF yields a value closer to 2/3 of the range—for example, 0xA800.
N VDD is a sampling of the regulated supply, VDD/2.
<<16 indicates a bit shift left by 16 bits.
When calculating the voltage of VDD_PADS (ADC_SEL = 4), V = (1/4) * VDD_PADS
When calculating the voltage of VDD (ADC_SEL = 5), V = (1/2) * VDD
Table 36 lists other specifications for the ADC Module not covered in Table 33.
Table 36. ADC Specifications
Parameter
VREF
Min.
1.19
Typ.
1.2
Max.
1.21
Unit
V
VREF output current
VREF load capacitance
Minimum input voltage
Maximum input voltage
0
1
10
VREF
mA
nF
V
V
Single-ended signal range
Differential signal range
Common mode range
Input referred ADC offset
0
- VREF
0
- 10
VREF
+ VREF
VREF
10
V
V
V
mV
Input Impedance
When taking a Sample
When not taking a Sample
1
10
M Ohm
Note:
The signal-ended ADC measurements are limited in their range and only guaranteed for accuracy in
the range 0 to VREF. The nature of the ADC's internal design allows for measurements outside of this
range (+/- 200mV), but the accuracy of such measurements are not guaranteed. The maximum input
voltage is of more interest to the differential sampling where a differential measurement might be
small, but a common mode can push the actual input voltage on one of the signals towards VDD.
Page 99
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